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MC10124 Quad TTL to MECL Translator
The MC10124 is a quad translator for interfacing data and control signals between a saturated logic section and the MECL section of digital systems. The MC10124 has TTL compatible inputs, and MECL complementary open-emitter outputs that allow use as an inverting/ non-inverting translator or as a differential line driver. When the common strobe input is at the low logic level, it forces all true outputs to a MECL low logic state and all inverting outputs to a MECL high logic state. Power supply requirements are ground, +5.0 Volts, and -5.2 Volts. Propagation delay of the MC10124 is typically 3.5 ns. The dc levels are standard or Schottky TTL in, MECL 10,000 out. An advantage of this device is that TTL level information can be transmitted differentially, via balanced twisted pair lines, to the MECL equipment, where the signal can be received by the MC10115 or MC10116 differential line receivers. The MC10124 is useful in computers, instrumentation, peripheral controllers, test equipment, and digital communications systems. * PD = 380 mW typ/pkg (No Load) * tpd = 3.5 ns typ (+ 1.5 Vdc in to 50% out) * tr, tf = 2.5 ns typ (20%-80%)
LOGIC DIAGRAM
5 6 7 10 11 Gnd = VCC (+5.0Vdc) = VEE (-5.2Vdc) = 4 2 3 1 12 15 13 14 PIN 16 PIN 9 PIN 8 A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week
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16 CDIP-16 L SUFFIX CASE 620 1 16 PDIP-16 P SUFFIX CASE 648 1 1 PLCC-20 FN SUFFIX CASE 775 10124 AWLYYWW MC10124P AWLYYWW MC10124L AWLYYWW
ORDERING INFORMATION
Device MC10124L MC10124P Package CDIP-16 PDIP-16 PLCC-20 Shipping 25 Units / Rail 25 Units / Rail 46 Units / Rail
DIP PIN ASSIGNMENT
BOUT AOUT BOUT AOUT AIN
COMMON STROBE BIN
MC10124FN
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
GND COUT DOUT DOUT COUT DIN CIN VCC
VEE
Pin assignment is for Dual-in-Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D).
(c) Semiconductor Components Industries, LLC, 2002
1
January, 2002 - Rev. 7
Publication Order Number: MC10124/D
MC10124
ELECTRICAL CHARACTERISTICS
Test Limits Pin Under Test 8 9 9 6 7 6 7 6 7 6 7 1 3 1 3 1 3 1 3 -1.060 -1.060 -1.890 -1.890 -1.080 -1.080 -1.655 -1.655 5.5 5.5 -1.5 -1.5 -0.890 -0.890 -1.675 -1.675 -0.960 -0.960 -1.850 -1.850 -0.980 -0.980 -1.630 -1.630 -30C Min Max 72 16 25 200 50 -12.8 -3.2 5.5 5.5 -1.5 -1.5 -0.810 -0.810 -1.650 -1.650 -0.890 -0.890 -1.825 -1.825 -0.910 -0.910 -1.595 -1.595 Min +25C Typ Max 66 16 25 200 50 -12.8 -3.2 5.5 5.5 -1.5 -1.5 -0.700 -0.700 -1.615 -1.615 Min +85C Max 72 18 25 200 50 -12.8 -3.2 Unit mAdc mAdc mAdc Adc mAdc Vdc Vdc Vdc Vdc Vdc Vdc ns t6+1+ t6-1- t7+1+ t7-1- t7+3- t7-3+ t1+ t1- 1 1 1 1 3 3 1 1 1.5 1.0 1.5 1.0 1.5 1.0 1.0 1.0 6.8 6.0 6.8 6.0 6.8 6.0 4.2 4.2 1.0 1.0 1.0 1.0 1.0 1.0 1.1 1.1 3.5 3.5 3.5 3.5 3.5 3.5 2.5 2.5 6.0 6.0 6.0 6.0 6.0 6.0 3.9 3.9 1.0 1.5 1.0 1.5 1.0 1.5 1.1 1.1 6.0 6.8 6.0 6.8 6.0 6.8 4.3 4.3
Characteristic Negative Power Supply Drain Current Positive Power Su y os e o e Supply Drain Current Reverse Current Forward Current Input Breakdown Voltage Clamp Input Voltage High Output Voltage Low Output Voltage High Threshold Voltage Low Threshold Voltage Switching Times Load) (50
Symbol IE ICCH ICCL IR IF BVin VI VOH VOL VOHA VOLA
Propagation Delay (+3.5Vdc to 50%)1
Rise Time Fall Time
(20 to 80%) (20 to 80%)
1. See switching time test circuit. Propagation delay for this circuit is specified from +1.5Vdc in to the 50% point on the output waveform. The +3.5Vdc is shown here because all logic and supply levels are shifted 2 volts positive.
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MC10124
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts) @ Test Temperature -30C +25C +85C Pin Under Test 8 9 9 6 7 6 7 6 7 6 7 1 3 1 3 1 3 1 3 6,7 6,7 6,7 6,7 6 6 6 6 +6.0 V t6+1+ t6-1- t7+1+ t7-1- t7+3- t7-3+ t1+ t1- 1 1 1 1 3 3 1 1 7 7 6 6 6 6 6 6 Pulse In 6 6 7 7 7 7 7 7 7 7 7 7 Pulse Out 1 1 1 1 3 3 1 1 5,7,10,11 6 5,7,10,11 6 6 7 5,6,7,10,11 VIH +4.0 +4.0 +4.0 VILmax +0.40 +0.40 +0.40 VIHA' +2.00 +1.80 +1.80 VILA' +1.10 +1.10 +0.90 VF +0.40 +0.40 +0.40
TEST VOLTAGE APPLIED TO PINS LISTED BELOW VIH VILmax VIHA' VILA' VF Gnd 16 16
5,6,7,10,11,16
Characteristic Negative Power Supply Drain Current Positive Power Su y Drain os e o e Supply a Current Reverse Current Forward Current Input Breakdown Voltage Clamp Input Voltage High Output Voltage Low Output Voltage High Threshold Voltage Low Threshold Voltage Switching Times (50 Load)
Symbol IE ICCH ICCL IR IF BVin VI VOH VOL VOHA VOLA
16 16 16 16 5,7,10,11,16 6,16 16 16 16 16 16 16 16 16 16 16 +2.0 V 16 16 16 16 16 16 16 16
Propagation Delay (+3.5Vdc to 50%)1
Rise Time Fall Time
(20 to 80%) (20 to 80%)
1. See switching time test circuit. Propagation delay for this circuit is specified from +1.5Vdc in to the 50% point on the output waveform. The +3.5Vdc is shown here because all logic and supply levels are shifted 2 volts positive.
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MC10124
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts) @ Test Temperature -30C +25C +85C Pin Under Test 8 9 9 6 7 6 7 6 7 6 7 1 3 1 3 1 3 1 3 6 7 VR +2.40 +2.40 +2.40 VCC +5.00 +5.00 +5.00 VEE -5.2 -5.2 -5.2 II -10 -10 -10 (mA) Iin +1.0 +1.0 +1.0
TEST VOLTAGE APPLIED TO PINS LISTED BELOW VR VCC 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 +7.0 V VEE 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 -3.2 V 8 8 8 8 8 8 8 8 6 7 6 7 II Iin Gnd 16 16
5,6,7,10,11,16
Characteristic Negative Power Supply Drain Current Positive Power Su y Drain os e o e Supply a Current Reverse Current Forward Current Input Breakdown Voltage Clamp Input Voltage High Output Voltage Low Output Voltage High Threshold Voltage Low Threshold Voltage Switching Times (50 Load)
Symbol IE ICCH ICCL IR IF BVin VI VOH VOL VOHA VOLA
16 16 16 16 5,7,10,11,16 6,16 16 16 16 16 16 16 16 16 16 16 +2.0 V 16 16 16 16 16 16 16 16
Propagation Delay (+3.5Vdc to 50%)1
t6+1+ t6-1- t7+1+ t7-1- t7+3- t7-3+ t1+ t1-
1 1 1 1 3 3 1 1
9 9 9 9 9 9 9 9
Rise Time Fall Time
(20 to 80%) (20 to 80%)
1. See switching time test circuit. Propagation delay for this circuit is specified from +1.5Vdc in to the 50% point on the output waveform. The +3.5Vdc is shown here because all logic and supply levels are shifted 2 volts positive. Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50-ohm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner.
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MC10124
SWITCHING TIME TEST CIRCUIT
Vout NAND +7.0 Vdc 0.1 F Coax Coax Vout AND
Vin
+6.0 Vdc
VCC
Coax
0.1 F
25 F
Input Pulse Generator
5 6 7 10 11
4 2 3 1 12 15 13 14 16 8 0.1 F Unused outputs connected to a 50-ohm resistor to ground.
Input Pulse t+ = t- = 5.5 0.5 ns (10 to 90%)
0.1 F 50-ohm termination to ground located in each scope channel input. All input and output cables to the scope are equal lengths of 50-ohm coaxial cable. Wire length should be < 1/4 inch from TPin to input pin and TPout to output pin.
25 F
+ 2.0 Vdc
VEE
-3.2 Vdc
NOTE: All power supply and logic levels are shown shifted 2 volts positive.
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MC10124
PACKAGE DIMENSIONS
PLCC-20 FN SUFFIX PLASTIC PLCC PACKAGE CASE 775-02 ISSUE C
B -N- Y BRK D -L- -M- W D X V A Z R 0.007 (0.180) 0.007 (0.180)
M
0.007 (0.180) U
M
T L-M
M
S
N
S S
0.007 (0.180)
T L-M
N
S
Z
20
1
G1
0.010 (0.250)
S
T L-M
S
N
S
VIEW D-D T L-M T L-M
S
N N
S
H
0.007 (0.180)
M
T L-M
S
N
S
M
S
S
K1 K
C
E 0.004 (0.100) G G1 0.010 (0.250) S T L-M J -T-
SEATING PLANE
F VIEW S
NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
0.007 (0.180)
M
T L-M
S
N
S
VIEW S
S
N
S
DIM A B C E F G H J K R U V W X Y Z G1 K1
INCHES MIN MAX 0.385 0.395 0.385 0.395 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --0.025 --0.350 0.356 0.350 0.356 0.042 0.048 0.042 0.048 0.042 0.056 --0.020 2_ 10 _ 0.310 0.330 0.040 ---
MILLIMETERS MIN MAX 9.78 10.03 9.78 10.03 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --0.64 --8.89 9.04 8.89 9.04 1.07 1.21 1.07 1.21 1.07 1.42 --0.50 2_ 10 _ 7.88 8.38 1.02 ---
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MC10124
PACKAGE DIMENSIONS
CDIP-16 L SUFFIX CERAMIC DIP PACKAGE CASE 620-10 ISSUE T
-A-
16 9
-B-
1 8
C
L
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. DIM A B C D E F G H K L M N INCHES MIN MAX 0.750 0.785 0.240 0.295 --0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 --5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01
-T-
SEATING PLANE
N E F D G
16 PL
K M J
16 PL
0.25 (0.010)
M
M
TB
S
0.25 (0.010)
TA
S
-A-
16 9
PDIP-16 P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R
B
1
8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
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MC10124
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-0031 Phone: 81-3-5740-2700 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative.
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MC10124/D

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